Our  real  work  is  doing  high-level  manipulation  and  perception
studies.  We  must  examine  the question of getting new devices with
some suspicion in order to justify its contribution to research.   We
want  to  examine  the  cost  of getting a PDP-11 and the cost of not
getting one.

One of the purposes of getting a PDP-11 is to make credible  advanced
assembly  devices.   This  has the benefit of getting general support
for AI and robotics, since as I argue in the  proposal  and  progress
report,  the  general computerization of industry and the programming
of robots (which would be done  on  a  central  time-sharing  system)
requires  the  most  sophisticated of AI techniques.  It also has the
advantage of increased problem stimulation; realistic problems  often
have  research  interest  (eg  visual feedback).  We expect increased
interchange with industry if we have something that looks  promising.
We  cannot  expect  that industrial research people can have the same
confidence that we have that converting from a big machine to a small
one  will  raise  no  difficulties, nor that they be able to persuade
their management that this is so.

A principle benefit is to increase independence of  robotics  systems
from  the  general system and system transitions.  The present system
is quite inadequate: we can have no user interrupts on the PDP-6,  if
we  have  the  PDP-6  for  long  without  releasing it, we tie up the
time-sharing system.  Changes for our benefit interact  heavily  with
the  general  system.   We  have been unable to get even minor system
changes (shuffling space war jobs to the bottom of core was done only
for  the  XGP) for obvious reasons; in choosing between something for
the whole system or something  special  for  robotics,  anyone  would
choose  general  system improvements.  If there is a change to TENEX,
which would be beneficial in many ways for  us,  the  space  war  and
other  special  features  may  be  the  last  stabilized parts of the
system.

There are several benefits which come from increased computing power.
The  PDP-11/45  is well-suited for vision.  A 3 module which requires
three minutes machine time, getting 10% of the machine,  requires  30
minutes  real  time.   There  is  a theorem that anything complicated
which requires more than 5 minutes real time per trial is  not  going
to  get  debugged,  becaues it won't go through enough generations of
change.  On the correlation inner loop, we estimated a  factor  of  5
increase  in  speed for the 11/45 over the PDP-10.  There is also the
utilization factor. To a certain extent,  we  offset  that  by  using
canned  images  and  intermediate result files, but that goes only so
far,  particularly  since  we  are  starting   to   use   interactive
strategies.  As  a  consequence  of  cutting computation time, we can
improve visual  feedback,  since  there  will  be  less  time  before
activation,  and  less time to completion. Similarly, certain modules
which now are too expensive, can be used as subsystems.

The problems are:
hardware interfacing:
a) we need an i/o bus interface for controlling the 11.
Poole says that a two-way interface through the 167 is a few days work
b) change over devices.  This will require an a/d and multiplexer.
Otherwise, it is not terribly difficult to go from one bus to the other,
but requires time.  Total 2 months
c)memory interfacing for buffer memory 2 months.

software interfacing:
a) pdp-10 system code
b) small operating system-as much as possible from pdp-10
c) languages-assembler,BLISS-11,SAIL?  primarily from pdp-10
d) RAID 
e) arm conversion-servo being done by JPL, planning must be done
f) vision conversion

hidden costs
a) diversion from research
b) two languages
c) two systems, imperfect communication

Note that best gains in response if both assembling and debugging
rest in pdp-11



SUMMARY
Cost of not getting pdp-11	cost of getting pdp-11
system changes  3 months	system effort 2 man years
research ineff  25%		research ineff 25%
				hardware $50k

PDP 11/45 CONFIGURATION 

11/45 CC	MINIMUM CPU CONFIGURATION
		16K CORE W/PARITY, FLEXOWRITER		$26,950

KT11-C		MEMORY MANAGEMENT			$3,900

FP11-B		FLOATING POINT BOX			$4,900

KW11-P		REAL TIME CLOCK				$600


10% DISCOUNT TO STANFORD

???		PROGRAMMABLE STACK


M792		CUSTOMIZED BOOTSTRAP LOADER (ROM)	$300

DL-10		PDP-10 MEMORY BUS TO UNIBUS

EXTRA MOS FROM INTEL .84 CENTS/BIT
USE AS TV MEMORY 64K BY 18 BITS				$10,000
CONFIGURE THIS AS TV BUFFER AND RANDOM
ACCESS, 4 WDS WIDE FOR TV, 4 WAY SELECTOR
FOR RANDOM ACCESS, POSSIBLE ERROR CORRECTION
(72 BITS FOR 64 BIT SINGLE ERROR CORRECTION)
INTERFACE: 2 WAY SELECTOR TV OR PDP-11.

POSSIBLE HOME-BREW MAP (TABLE LOOKUP)
ASSIGN I/O ADDRESSES TO LOAD THROUGH
UNIBUS.  128 WDS BY 16 BITS AT 10 CENTS/BIT		$200 +DESIGN+FABRICATION
NOT SERIOUS CANDIDATE

KEN STIKOWSKI  216-368-2818  CASE

1.  RELIABILITY OF MOS MEMORY
CASE HAS HAD BIG PROBLEMS WITH MOS (KEN STIKOWSKI).
SOME DIPS WERE CHANGED.  PROBLEMS REMAINING SEEM TO
BE NOISE-RELATED, COMING WHEN DISK TRANSFERS, ETC
ARE GOING ON. 
2.  STIKOWSKI LIKES THE ASSEMBLER.
DEBUGGER IS OCTAL
3.  MEMORY SEGMENTATION IS ALMOST UNUSABLE.
AT PAGE FAULTS, THE PC AND OTHER REGISTERS
MAY BE CHANGED BY AUTO-INCREMENTS AND LOOKAHEAD.
THEY MUST BE RECONSTRUCTED LABORIOUSLY BY SOFTWARE.
IF WE DO NOT DO DEMAND PAGING, WE MAY GET BY USING
IT AS AN EXPENSIVE MAP.
4.  ONLY 8 OF THE 16 PAGES ARE USABLE.  THE DATA
PAGES ARE NOT USABLE BECAUSE THE MARK INSTRUCTION
MAY GO ON THE PDL.  ONLY KERNEL AND USER MODES ARE
USABLE, ACCORDING TO LYNCH AT CASE.
5.  SOFTWARE IS STANDARD 11/20 WHICH DOES NOT SUPPORT MAPPING OR USE
MORE THATN 65K.
6.  FORTRAN IS INTERPRETIVE-DOES NOT PUT OUT MACHINE CODE.
7.  MANY PEOLE WRITING PDP-11 SOFTWARE.

1. CORE 850 NSEC CYCLE TIME
16K INTERLEAVED, EFFECTIVE TIME 650 NSEC